CPU Performance Modeling (Lead & ICs)

At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. As our CPU Performance Modeling Lead, you will own the performance modeling infrastructure and methodology that drives every architectural decision we make — from early pathfinding through tape-out and post-silicon correlation.
THE ROLE
Design, develop and own Nuvacore’s cycle-accurate CPU performance simulator — its architecture, fidelity, and long-term roadmap — as the authoritative reference model for the design team.
Lead microarchitectural exploration across all major CPU domains: frontend (fetch, decode, branch prediction), out-of-order engine (rename, dispatch, execution), and memory subsystem (caches, prefetchers, TLBs, coherence).
Drive model-to-RTL correlation through all execution phases; own debug and resolution of performance miscorrelation between the performance model, RTL simulation, and post-silicon results.
Collaborate closely with design, verification, compiler, and system software teams to align architecture decisions with implementation constraints and software stack realities.
Mentor engineers across the performance team; provide technical leadership on modeling methodology, simulation infrastructure, and analysis tooling.
Contribute to IP development through patents and, where applicable, external publication

REQUIREMENTS — MUST HAVE
MS in Computer Architecture, Computer Engineering, or related field (PhD preferred).
20+ years (Lead) or 8+ years (ICs) in CPU microarchitecture and/or performance engineering.
20+ years (Lead) or 8+ years (ICs) of hands-on experience with cycle-accurate C++ CPU performance simulators (e.g. gem5 or equivalent in-house tools).
Deep expertise in at least one of: branch prediction, fetch/decode, rename/dispatch, OOO execution, memory subsystem, or prefetchers.
Strong C++ and Python / Perl skills; ability to write and analyze assembly for microarchitectural test cases.
Proven track record driving performance from pathfinding through silicon (RTL correlation and/or post-Si debug).
Experience in RISC-V or ARM64 or x86 ISA.
Strong track record in identifying ideas to improve power/performance/area (PPA) of CPUs.
Experience developing trace-based and execution-driven CPU performance simulators.
REQUIREMENTS — NICE TO HAVE
Experience with compiler optimizations and hardware/software co-design.
Published work or filed patents in CPU performance or microarchitecture.
Prior principal-level role at a CPU design organization.
The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.