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The Posting
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer
- 12+ years of Design Verification experience with SV/UVM
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantag
We’re doing work that matters. Help us solve what others can’t.
Facts
- Source
- Workday
- External id
- R53284
- Location
- BANGALORE, India
- Remote
- Not stated
- Employment
- Full time
- Posted
- 19 Feb 2026
- First seen
- 25 Oct 2026, 06:49
- Last seen
- 1 Nov 2026, 04:19
- Status
- Not yet added
- Posting id
- 01b8d981-609a-5d20-be73-ffd331877c41