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The Posting
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl/Tcl scripting and automation
We’re doing work that matters. Help us solve what others can’t.
Facts
- Source
- Workday
- External id
- R50560
- Location
- BANGALORE, India
- Remote
- Not stated
- Employment
- Full time
- Posted
- 1 Sep 2025
- First seen
- 25 Oct 2026, 06:49
- Last seen
- 1 Nov 2026, 04:19
- Status
- Not yet added
- Posting id
- d1788d05-1cac-5df6-9cb8-73166dd8a859