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Analog DevicesDurham, NC, United States. Full time.

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DesignAutomationVerification and ValidationOperations planningSystemVerilogUniversal Verification Methodology (UVM)Working with minimal supervisionFirmwareRequirements traceabilityVerilogDebuggingScripting and automationQuantitative data analysisBachelor of Science in Electrical EngineeringExport control regulations

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