See what your resume is missing for ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years at Cisco

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CiscoBangalore, India. Full time.

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ASIC designVerilogSystemVerilogUniversal Verification Methodology (UVM)Nonprofit experienceData centerEnterprise networkingRouting and switchingLifecycle marketingDebuggingSilicon bring-upFormal verificationDirect Response MarketingEmailLaw Enforcement Experience

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