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CadenceNOIDA, India; BANGALORE, India. Full time.

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Design for TestRTL designComputer architectureStatic Timing AnalysisStatistical power analysisDebuggingVerilogSystemVerilogJTAGProblem-solving skillsProfessional Engineer (PE) licenseData structures and algorithmsExcellent verbal and written communicationCommunication and presentation skillsDiscrete logic design

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