See what your resume is missing for ASIC Design Verification Engineer || Verilog, UVM, Testbench | Emulation || Exp 7+ years at Cisco
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CiscoBangalore, India. Full time.
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ASIC designVerilogUniversal Verification Methodology (UVM)Nonprofit experienceEnterprise networkingRouting and switchingHardware designTest automation frameworksDocument verificationTeam leadershipTrainingSoftware testing methodologiesDirect Response MarketingEmailLaw Enforcement Experience
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