See what your resume is missing for Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years at Cisco
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CiscoBangalore, India. Full time.
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ASIC designVerilogUniversal Verification Methodology (UVM)Technical LeadershipProblem solvingSystemVerilogC++ScriptingOperations planningMentoringSolidWorksDebuggingInterpersonal SkillsCommunicationEmail
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