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Astera LabsSan Jose, CA, United States.
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Design VerificationAI infrastructureConnectivity solutionsPCIeUALinkUniversal Verification Methodology (UVM)SystemVerilogTestbench developmentPCIe Gen 6UCIDebuggingFunctional and code coverageAutomationBachelor of Science in Electrical EngineeringDegree in Electrical Engineering
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